Cortex X925 has a 64 KB L1 data cache with 4 cycle latency like A725 companions in GB10, but takes advantage of its larger power and area budget to make that capacity go further. It uses a more sophisticated re-reference interval prediction (RRIP) replacement policy rather than the pseudo-LRU policy used on A725. Bandwidth is higher too. Arm’s technical reference manual says the L1D has “4x128-bit read paths and 4x128-bit write paths”. Sustaining more than two stores per cycle is impossible because the core only has two store-capable AGUs. Loads can use all four AGUs, and can achieve 64B/cycle from the L1 data cache. That’s competitive against many AVX2-capable x86-64 CPUs from a few generations ago. However, more recent Intel and AMD cores can use their wider vector width and faster clocks to achieve much higher L1D bandwidth, even if they also have four AGUs.
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在开源社区，Qwen3.5系列四款开源小模型（Qwen3.5-0.8B、2B、4B、9B）表现亮眼，上线后不仅获得马斯克的点赞，也在AI开源社区与模型托管平台Hugging Face上热度飙升，包揽趋势榜单前8位。
自衝突開始以來，科威特已有九人喪生，包括六名美軍、兩名科威特軍人及一名平民。
Безумие, что эта война продолжается